1. Field of the Invention
Embodiments herein generally relate to placing items and routing wiring pursuant to integrated circuit specifications to create an integrated circuit design in a process that pauses the wiring routing process to allow repositioning of previously placed items to make the wiring routing process more productive.
2. Description of Related Art
As described in U.S. Patent Publication 2007/0089079 (the complete disclosure of which is incorporated herein by reference), the blocks and sub-blocks that form an IC or a board can be divided into different hierarchy levels: the device level comprising elements such as transistors, diodes, and capacitors, the book level comprising elements from a library such as gates (i.e. NAND and NOR circuits) and latches, the macro level comprising complex elements like adders and dividers, the unit level comprising elements from the macro level (i.e. adder) and the chip level comprising elements from the macro and the unit level (i.e. Floating Point Unit), and the board level comprising elements such as integrated circuits.
Both placement and routing are usually performed sequentially. In an iteration step the layout is optimized for various goals while ensuring signal integrity and compliance to various design rules related to the semiconductor manufacturing process. Examples of placement optimization goals are minimizing the wire-length between the various blocks as the signal delay increases with the wire length, and maximizing the wire density to save chip area. Examples of routing optimization goals are minimizing the wire length, and having the same or similar length for certain wires. If it is not possible to achieve the optimization goals then the current layout is dropped, the design of the IC will be changed and the placement and routing process is started again. With the enduring trend of devices (e.g. transistors) and books and macros (e.g. gates) becoming smaller and faster, IC designs are being limited by the delays of the wires connecting the devices and macros rather than by their area.
As technology moves to advanced processes, routing becomes more dominant in the physical design process. The general concept of good placement will yield “good routing” might not hold in advanced technologies. Since power, noise, and timing are more difficult to solve, and routing has a bigger impact on these violations.